workshop

What's inside the black box? Compiler developments for HPC

Lead: Pawel K. Radtke

Contributors: Nick Brown, Maurice Jamieson, Shounak Chakraborty, Pawel K. Radtke

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Description

What’s inside the black box? Compiler developments for HPC brings together compiler developers, standards contributors, and HPC practitioners to discuss how recent advancements in compilation techniques impact the performance, portability, and correctness of scientific codes on today’s increasingly heterogeneous systems. Speakers from academia and industry will highlight emerging compiler infrastructures, advances in optimisation, directive-based programming, data layout, accelerator support, tools for understanding and guiding optimisation decisions, and domain-specific approaches that raise productivity while preserving trust, reproducibility, and predictable behaviour in high-performance computing workflows for real-world scientific applications.

Compiler pipelines for scientific computing on AI accelerators | Nick Brown

We are seeing a range of new accelerator hardware becoming available. Whilst the majority of this has been primarily designed for AI workloads, the underlying capabilities can be leveraged more widely for scientific computing applications. However, the devil is in the detail when it comes to porting these codes to such architectures, with programmers having to master bespoke, often esoteric, programming tools and models. I will present our compiler approach which hides this complexity from the programmer. Leveraging xDSL and MLIR, we develop building blocks that are common across architectures and share infrastructure for as long as possible.

ExaHyPE-DSL: Integrating a Python-based DSL with the MLIR/LLVM compiler ecosystem | Maurice Jamieson

ExaHyPE is an open-source simulation engine to write solvers for hyperbolic partial differential equation (PDE) systems. ExaHyPE-DSL enables programmers to express their intentions in a high-level domain-specific language (DSL) that is close to the problem domain, which is then progressively lowered via the LLVM toolchain to executable code. This approach makes compiler optimisation decisions transparent for heterogeneous scientific computing by exposing the generated MLIR and its pass pipeline. We introduce the Python-based DSL and discuss the code generator for MLIR and associated passes, highlighting the benefits of the approach and key challenges encountered.

From MLIR to Silicon: How Compilers Lower Accelerator Code | Shounak Chakraborty

Attaining peak performance in modern scientific computing increasingly requires performance engineers to navigate a highly fragmented hardware landscape, stretching from dense GPU clusters to specialised spatial accelerators. While high-level programming models and domain-specific languages have expanded developer velocity, they simultaneously widen the semantic chasm down to physical execution units. This talk demystifies how modern compiler infrastructures bridge this gap through the lens of the Multi-Level Intermediate Representation (MLIR) ecosystem. We walk through the mechanics of progressive lowering, demonstrating how high-level abstractions are systematically translated through specialised dialects without losing crucial parallel intent. We expose the physical act of bifurcation at heterogeneous boundaries, illustrating how a single application is split into a host orchestration pipeline and an isolated device execution kernel. Finally, we analyse the microarchitectural realities of accelerator execution, contrasting traditional CPU SIMD vectorisation with massively parallel SIMT thread grids. By diagnosing the precise compiler-level origins of severe runtime performance cliffs—such as branch divergence serialisation and non-coalesced memory bus starvation—this talk equips HPC practitioners with the structural mental models needed to write fundamentally compiler-friendly code for modern heterogeneous silicon.

Compiler-supported reduced precision and AoS-SoA transformations for heterogeneous hardware | Pawel K. Radtke

We evaluate AoS-to-SoA transformations over reduced-precision data layouts for a particle simulation code on several GPU platforms: We hypothesize that SoA fits particularly well to SIMT, while AoS is the preferred storage format for many Lagrangian codes. Reduced-precision (below IEEE accuracy) is an established tool to address bandwidth constraints, although it remains unclear whether AoS and precision conversions should execute on a CPU or be deployed to a GPU if the compute kernel itself must run on an accelerator. On modern superchips where CPUs and GPUs share (logically) one data space, it is also unclear whether it is advantageous to stream data to the accelerator prior to the calculation, or whether we should let the accelerator transform data on demand, i.e. work in-place logically. We therefore introduce compiler annotations to facilitate such conversions and to give the programmer the option to orchestrate the conversions in combination with GPU offloading. For some of our compute kernels of interest, Nvidia’s G200 platforms yield a speedup of around 2.6 while AMD’s MI300A exhibits more robust performance yet profits less. We assume that our compiler-based techniques are applicable to a wide variety of Lagrangian codes and beyond.